It must be stiff enough to not drop much when feeding the base, to it should conduct at least 100uA (Since Ic = 1mA and beta=100, Ib = 10uA, so 100uA is the minimum for a stiff divider). So the resistor divider biasing the base must be at 1.7V. Since the typical active transistor has a voltage drop of about 0.7 volts, the base will be at 1.7V of voltage. Emitter feedback will take care of beta increases with temperautre. It's true that emitter current is not equal to collector current, but with a beta > 100 it is good enough. With a 1K DC resistor load, the voltage at the emitter will be 1V, since = 1V. We choose 1K as emitter resistor, and later we will add a capacitor coupled load for AC amplification. In order to get 50 voltage gain, the emitter resistor should be 4.5K/50 = 90, which is not good from a bias stability viewpoint. That load must be the parallel combination of load resistance and collector resistor. A good collector resistance will then be 4.5K, since = 4.5 volts drop. So let us choose a collector current of 1mA and a collector voltage of 4.5volts. To get a good swing, the bias voltage could be around 4.5 volts, at the middle of the working voltage. A collector current Ic=1mA is not bad for a 2N3904 (typical beta > 100, even if Ic=3-5mA would be better, it's somewhat wasteful). You want a -50 voltage gain, and use little power and one 2N3904. A practical case (I invented the parameters first, and built the amp later): you want to amplify a 50mv top amplitude signal with bandwidth from 100Hz to 100kHz and 3K input impedance. There are cures for all these restrictions (small signal -> feedback, AC -> diff amp, gain -> active load, bw -> cascode, impedance -> buffering / bootstrapping) but all require more transistors or components. They are useful for small signal, AC coupled, medium gain inverting amplifiers at moderate frequencies and medium input-output impedances. For a given quiescent drain current, how can you quantify the voltage swing at a given load? Do people usually calculate that as part of their design? Rules of thumb? Make RL > RD?ĬE amplifiers are a basic building block. To me, it seems like there are some simultaneous equations going on(?). As the voltage at the drain changes, current is either driven into or pulled from the load. But now if you attach a given load (through a coupling cap), whenever the input changes (above a certain frequency), the transistor now "sees" a load attached to its drain. ![]() That current has to come from somewhere so, in the common source case, it is pull through the drain resistor RD which causes a greater drop across that resistor, swinging the voltage at the drain. When you change Vgs, you change the current that must flow. The equation relating drain current to Vgs tells us that for a given overdrive voltage (Vgs-Vt), the conducting channel must conduct some current. Everything makes sense in the non loaded case. I've been having a really hard time selecting a proper DC drain/collector current for a given load. In the case of a common source FET amplifier or common emitter BJT amplifier, what would be your general steps to properly establishing a bias point? Thanks. I know this is a very open ended question, so maybe I should narrow it down. ![]() Most of the literature I've seen is academic in nature, and while true, seems a bit impractical(?) In fact, I've seen many forum posts that say "Here is how you would solve this, but we would never do it this way in the real world".and then do not explain how they would do it. I've hunted around many forums and many many documents trying to figure out what a good practical approach is to designing transistor circuits with values available in the datasheet and with a given set of constraints. By this I mean: Many times we are given constants that wouldn't be provided in a real datasheet (k, a trans-conductance parameter, for example) OR we are given a set of assumptions that seemingly come out of thin air (like assume the drain current is X). These exercises are all good and well but I still feel like there is a disconnect between what we learn from our textbook (in this case Sedra/Smith) and how "real engineers" design transistor circuits the real world. Hi everyone, As a fourth year EE student, I've solved many problems with transistors, doing bias calculations, small signal modeling etc.
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